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1/20 STA001 november 2002 this is preliminary information on a new product now in development. details are subject to change without notice. n single chip receiver for satellite digital transmission n superheterodyne receiver with if output n high input intercept point, low mixer noise n 54db if vga gain range n adjustable rf gain n adjustable if gain n integrated rf vco n integrated if vco n integrated synthesizer n i 2 cbus compatible programming interface n unregulated 2.7 v to 3.3v voltage supply n low cost external components description the STA001 is an rf ic using stmicroelectronics hsb2 high speed bipolar technology for one chip so- lution for the starman digital satellite radio receiver. the STA001 is assembled in a tqfp44 package. the frontend architecture is a double conversion re- ceiver (see block diagram) . the chip includes all the rf functions up to low if and manages the signals to and from the baseband. tqfp44 ordering number: STA001 product preview rf front-end for digital radio block diagram xtal1, xtal2 channel selection m_clk differential single ended flt2 tk2, ntk2 lni, nlni sip, sin agc1, agc2 osc 3.68mhz 113.23khz scl sda 14.72mhz phase detector charge pump : 1034 2nd pll :130 vco 1338.14 - 1375.4 mhz 117.0806 mhz sop, son charge pump phase detector :363.625- 373.75 1st pll vco v dd1 v ss1 rf mixer if1 buffer vga if1 to if2 mixer if2 buffer flt1 ce 1.8366 mhz tlck lock detector :4 enrfosc buffer tk1, ntk1 supply2 :pll1 + crystal osc . supply3 :dig. supply4 :if1, if2 &pll2 supply1 :rf gadj1, gadj2 i2cbus interface ref xosel mux padj1, padj2 lna rxi, nrxi v dd2 v ss2 v dd4 v ss4 v dd3 v ss3 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 2/20 pin connection (top view) pin function n pin function 1 vdd1 positive supply 1 2 sip saw filter input connection 3 sin saw filter input connection 4 vss1 negative supply 1 5 lni rf input 6 nlni rf input 7 vss1 negative supply 1 8 nc not connected 9 padj1 rf gain adjust connection 1 10 padj2 rf gain adjust connection 2 11 enrfosc rf oscillator enable 12 vdd2 positive supply 2 13 tk1 1st pll tank connection 1 14 ntk1 1st pll tank connection 2 15 vdd2 positive supply 2 16 flt1 1st pll loop filter connection 17 vss2 negative supply 2 18 xtal1 quartz oscillator connection 1 19 xtal2 quartz oscillator connection 2 20 ref external optional tcxo input 21 xosel internal/external xo selection 22 tlck lock detector output 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 vdd1 sip sin vss1 lni nlni vss1 n.c. padj1 padj2 enrfosc vdd2 tk1 ntk1 vdd2 flt1 vss2 xtal1 xtal2 ref xosel tlck flt2 vdd4 tk2 ntk2 vdd4 agc2 agc1 vss4 son sop vss4 m_clk2 m_clk1 vss3 sda scl vdd3 ce gadj2 gadj1 nrxi rxi d97au602 12 13 14 15 16 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
3/20 STA001 absolute maximum ratings operating conditions 23 m_clk2 master clock differential output 1 24 m_clk1 master clock differential output 2 25 vss3 negative supply 3 26 sda data serial input 27 scl clock input 28 vdd3 positive supply 3 29 ce chip enable 30 gadj2 if gain adjust connection 2 31 gadj1 if gain adjust connection 1 32 nrxi low if signal output 2 33 rxi low if signal output 1 34 flt2 2nd pll loop filter connection 35 vdd4 positive supply 4 36 tk2 2nd pll tank connection 37 ntk2 2nd pll tank connection 38 vdd4 positive supply 4 39 agc2 vga control pin 2 40 agc1 vga control pin 1 41 vss4 negative supply 4 42 son saw filter output connection 43 sop saw filter output connection 44 vss4 negative supply 4 symbol parameter value unit t stg storage temperature -40 , +125 c t oper operative ambient temperature -20 , +85 c v max maximum voltage on any pin (with the exception of ce, sda, sdl) vdd+0.3 v v min minimum voltage on any pin gnd-0.3 v v maxi maximum voltage on pins ce, sda, sdl vdd+0.6 v vdd max minimum/maximum power supply between vdd 1,2,3,4 and vss 1,2,3,4 -0.3/5.5 v v esd electrostatic discharge voltage (esd) 2 kv symbol parameter value unit vdd operating voltage 2.7, 3.3 v t jun junction temperature -30, +95 c pin function (continued) n pin function obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 4/20 thermal data (1) according to jedec specification on a 4 layers board symbol parameter value unit r th j-amb thermal resistance junction to ambient (1) 45 c/w electrical characteristcs symbol parameter test condition min. typ. max. unit supply currents (t amb = 25, vdd = 3v) i cc1 current supplied by vdd1 powered circuits: lna, rf mixer, if buffer 9.5 14 17 ma i cc2 current supplied by vdd2 powered circuits: rf pll, crystal oscillator. enrfosc=high (ic rf osc. enabled), xosel=high (ic xo enabled) enrfosc=low (ic rf osc. disabled), xosel=high (ic xo enabled) enrfosc=high (ic rf osc. enabled), xosel=low (ic xo disabled) enrfosc=low (ic rf osc. disabled), xosel=low (ic xo disabled) 8.5 3 7.5 2 10 5 9 4 12 6 11 5 ma ma ma ma i cc3 current supplied by vdd3 powered circuits: digital cells 12 15 18 ma i cc4 current supplied by vdd4 powered circuits: vga, if mixer, output buffer, if pll. v(agc1)=v(agc2)=1.2 (if gain =75db) 71114ma i tot i cc1 + i cc2 + i cc3 + i cc4 enrfosc=high (ic rf osc. enabled), xosel=high (ic xo enabled) enrfosc=low (ic rf osc. disabled), xosel=high (ic xo enabled) enrfosc=high (ic rf osc. enabled), xosel=low (ic xo disabled) enrfosc=low (ic rf osc. disabled), xosel=low (ic xo disabled) 40 34 39 34 50 45 49 44 61 55 60 54 ma ma ma ma i totsb standby i cc1 + i cc2 + i cc3 + i cc4 ce=gnd 100 m a lna, rf mixer and if1 buffer (t = 25, vdd-vss = 3v) bw i input signal bw 1452 1492 mhz bw o output signal bw 114 116.5 mhz g v voltage gain input lni, nlni pins; output sip, nip pins. r l = 200 w, padj1, padj2 floating 28 30 33 db obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
5/20 STA001 g vtrim minimum voltage gain input lni, nlni pins; output sip, nip pins. r l = 200 w, r ext =0 22 25 28 db z i input impedance r || c balanced, lni, nlni pins 75 0.2 w pf z o output impedance balanced, sip, sin pins 50 w r l input return loss lni, nlni pins 14 db iip3 input ip3 input lni, nlni pins; output sip, nip pins, r l =200 w, padj1, padj2 floating -20 -15 dbm iip3 trim input ip3 minimum gain input lni, nlni pins; output sip, nip pins, r l =200 w, r ext =0 on padj1, padj2 -19.5 -11.5 dbm 1dbcp input 1 db compression point input lni, nlni pins; output sip, nip pins, r l =200 w, padj1, padj2 floating -26 dbm 1dbcp tri m input 1 db compression point input lni, nlni pins; output sip, nip pins, r l =200 w, padj1, padj2 r ext =0 on padj1, padj2 -24 dbm nf noise figure contribution measurement conditions: input lni, nlni pins; output sip, nip pins. r s =50 w, r l =200 w, dsb, padj1, padj2 floating 5db nf trim noise figure contribution minimum gain measurement conditions: input lni, nlni pins; output sip, nip pins. r s =50 w, r l =200 w, dsb, r ext =0 on padj1, padj2 6.5 db if1 leak lo1 to if1 leakage -100 -25 dbm rf leak lo1 to rf leakage -100 -30 dbm v dc lni, nlni common mode dc voltage ac coupled to the balun v dd - 1.2 v dd -1 v dd - 0.8 v v dc sip, sin common mode dc voltage ac coupled to the saw filter v dd - 1.3 v dd - 1.1 v dd - 0.9 v if vga amplifier, if mixer and output buffer (t = 25, vdd-vss = 3v) bw i input signal bw 114 116.5 mhz bw o output signal bw 0.6 3.1 mhz g min minimum gain input lni, nlni pins; output sip, nip pins. rl=high impedance v(agc 1,2 )=0v 32 37 db g max maximum gain input lni, nlni pins; output sip, nip pins. rl=high impedance v(agc 1,2 )=3v 71 86 db i agc input current in agc control pin 10 m a z agc agc pin input impedance 600 k w electrical characteristcs (continued) symbol parameter test condition min. typ. max. unit obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 6/20 figure 1. typical if overall gain vs control voltage nf noise figure contribution measurement conditions: input sip, nip pins; output sop, nop pins. r s =50 w, r l =200 w, dsb, gain = 65db 9db 1dbcp input 1 db compression point gain = 65db -50 dbm 1dbcp fg input 1 db compression point full gain gain = 81db -66 dbm iip3 input ip3 gain = 65db -41 dbm iip3 fg input ip3 full gain gain = 81db -57 dbm z in input impedance balanced, sop, son pins 50 w z out output impedance balanced, rxi, nrxi pins (see fig. 9) 200 w v dc sop, son common mode dc voltage ac coupled to the saw filter v dd - 1.2 v dd -1 v dd - 0.8 v v dc rxi, nrxi common mode dc voltage v dd - 2.1 v dd - 1.36 v v dc gadj1, gadj2 common mode dc voltage v dd - 0.15 v dd - 0.12 v dd v z adj gain adjustment pins impedance balanced, gadj1, gadj2 pins 800 w bb leak lo2 to bb leakage obtained using low pass filter at the output -45 dbm if2 leak lo2 to if2 leakage obtained with saw filter connected to if port -100 -30 dbm im3 third order im product v out =1v ddp -30 dbc electrical characteristcs (continued) symbol parameter test condition min. typ. max. unit 0.7 0.75 0.77 0.79 0.8 0.82 0.84 0.86 0.88 0.9 v(agc1, agc2) (volt) 30 35 40 45 50 55 60 if total voltage gain (db) if gain (db) if total voltage gain (db) input sop,nop output rxi,nrxi 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 v(agc1, agc2) (volt) 60 65 70 75 80 85 90 if total voltage gain (db) if gain (db) if total voltage gain (db) input sop,nop output rxi,nrxi obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
7/20 STA001 electrical characteristcs (continued) symbol parameter test condition min. typ. max. unit crystal oscillator (t = 25, vdd-vss = 3v) v dc xtal1, xtal2 common mode dc voltage xosel high v dd - 1.1 v dd - 0.68 v plls, synthesizers (t = 25, vdd-vss = 3v) t s rf pll loop settling time within 1 khz final freq. offset, by using the loop filter of application board 1ms p n total phase noise contribution 100hz < d f < 1.84mhz, q rf_tank 3 20, q if_tank 3 20 1.6 deg rms f ref1 rf pll comparation frequency 3.68 mhz f ref2 if pll comparation frequency 113.23 khz p sp spurious power level*** rf pll, d f c =n*460khz n=1,2.. if pll, d f c =113.23khz -100 -50 -45 dbc dbc n prog1 rf pll selectable division ratios from ref1 to lo1, range covered by a 0.5 step, using a 14.72mhz quartz 1443 (first used 1454.5) 1506.5 (last used 1495) n prog2 rf pll selectable division ratios from ref1 to lo1, range covered by a 0.5 step, using a 14.725mhz quartz 1443 (first used 1454) 1506.5 (last used 1494.5) n fix if pll fixed division ratios from ref2 to lo2, 1 fixed +2 testing values 987 1034 1081 n ref1 ref1 division ratio from crystal oscillator to ref1 4 n ref2 ref2 division ratio from crystal oscillator to ref2 130 *** using loop filter as suggested in application board schematics rf vco (t = 25, vdd-vss = 3v) f lo1_1 lo freq. range using 14.72mhz quartz 1338.14 1375.4 mhz f lo1_2 lo freq. range using 14.725mhz quartz 1338.134375 to 1375.407031 mhz v flt1 freq. control voltage range pin flt1 v ss + 0.2 v dd - 0.2 v v dc tk1, ntk1 dc voltage enrfosc high v dd - 1.3 v dd - 1.1 v dd - 0.65 v z i input impedance r || c balanced, tk1, ntk1 pins 300 0.2 w pf obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 8/20 if vco (t = 25, vdd-vss = 3v) f lo2_1 lo freq. using a 14.72mhz quartz, min. and max. values are optional fixed frequency usable for testing purposes. 111.76 117.08 122.4 mhz f lo2_2 lo freq. using a 14.725mhz quartz, min. and max. values are optional fixed frequency usable for testing purposes. 111.8 117.12 122.44 mhz v flt2 freq. control voltage range flt2 pin v ss + 0.2 v dd - 0.2 v digital interface to mp (scl, sda, tlck) and xosel interface (t = 25, vdd-vss = 3v) input parameters (scl, sda) v ih digital input signals high v dd -1 v dd v v il low v ss v ss +0. 7 v i ih input current high 10 m a i il input current low -40 m a t t input edge transition 0.1 m s/v r in input resistance 190k w output parameters (tlck) v oh digital output signals high v dd - 0.5 v dd v v ol low v ss v ss +0. 5 v t r rise time cl=5pf 0.4 m s/v t f fall time cl=5pf 0.4 m s/v differential digital interface (m_clk1, m_clk2) (t = 25, vdd-vss = 3v) v oh digital output signals, v(m_clk1) - v(m_clk2) high 0.2 v v ol low -0.2 v v dc m_clk1, m_clk2 common mode dc voltage v dd - 1.12 v dd - 0.7 v t r rise time cl=5pf each pin 10 ns t f fall time cl=5pf each pin 10 ns z out output impedance balanced 500 w electrical characteristcs (continued) symbol parameter test condition min. typ. max. unit obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
9/20 STA001 xosel, ce, tlck, enrfosc truth table (low = gnd, high = vdd) f m_clk1 m_clk frequency using a 14.72mhz quartz 14.72 mhz f m_clk2 m_clk frequency using a 14.725mhz quartz 14.725 mhz additional digital interface (ce) (t = 25, vdd-vss = 3v) (low=gnd, high=vdd) v ih digital input signals high v ss +1. 8 v v il low v ss +1. 3 v t r ce power up time 2 m s t f ce power down time 6 m s pin type level result ce input high chip enabled low chip disabled xosel input high internal crystal oscillator selected low external tcxo connected on ref selected enrfosc input high internal rf oscillator selected low external rf oscillator connected on tk1, ntk1 pins tlck output high synth. locked low synth. unlocked additional optional interface information (ref) symbol parameter test condition min. typ. max. unit v dc ref dc voltage xosel low v dd - 1.1 v dd - 0.9 v dd - 0.7 v r in input resistance xosel low 70k w electrical characteristcs (continued) symbol parameter test condition min. typ. max. unit obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 10/20 functional description receiver chain the receiver chain transforms the rf frequency signals to an if signal at 1.84 mhz carrier directly usable by the channel decoder. in front of the STA001 ic it can be placed an external lna and a bandpass filter; the bandpass filter limitates the input bandwidth and guarantees a suitable rejection to the image frequency. the STA001 input stage is a lna working in the 1452-1492 mhz band. the rf signal is downconverted, using an active mixer, to a first if of 115.244 mhz. the first lo is tunable with a frequency step of 460 khz. the rf can be reduced 5db by an external trimmer/resistor connected between padj1 and padj2 pins. an if variable gain amplifier guarantees 54 db typical of gain range. using pins gadj1, gadj2, the output rx signal level can be decreased to the desired value by an external trimmer/resistor. moreover, the if chain can be configured to have a fixed gain by fixing statically control voltages on agc1 and agc2 pins (i.e. v(agc1)=vcc and v(agc2)=gnd), and by trimming the gain through connecting an external resistor between gadj1 and gadj2. by using an 800 ohm resistor connected between gadj1 and gadj2, for example, a typical 56 dbs if static gain is obtained. the first if signal, having a bandwidth of 2.5 mhz, shaped by an external saw filter, is downconverted to a second if of 1.84 mhz. a differential clock output at 14.72 mhz is available to be used from the baseband. synthesizers, pll, charge pump and vcos the first voltage controlled oscillator is controlled by an integrated pll and it's able to cover a frequency range of 37mhz with a step size of 460 khz. the second voltage controlled osc illator pr oduces a fixed 117.08mhz frequency controlled by a second inte- grated pll. moreover, the 2nd pll is able to select 2 other fixed frequencies, i.e. 111.76mhz and 122.4mhz, suitable for application test. the other components of the first pll synthesizer are a low frequency programmable divider and a dual mod- ulus prescaler; a fixed dividers is instead used to synthesize the second vco frequency. other fixed internal dividers are used to get the comparation frequencies of both loops. channel selection is made through the i 2 cbus interface , directly from the m p. power supplies the chip operates from an unregulated power supply of 2.7 to 3.3 volts. all interface circuits to the baseband chips are operating between these supplies unless otherwise specified. interface specification all the interface voltage levels to the micro controller are referenced to the supply voltage of the interface power supply (gnd) . the interface voltage levels are therefore fully compatible with the base band circuits. the digital levels are all cmos threshold compatible with the exception of m_clk1, m_clk2 pins (ecl type). for completeness all other interface signals are also included. i 2 c bus interface data transmission from microprocessor to the STA001 takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected to sda and scl). obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
11/20 STA001 data validity the data on the sda line must be stable during the high period of the clock. the high to low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. byte format every byte transferred on the sda line must contains bits. each byte must be followed by an acknowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a resistive high level on the sda line during the acknowledge clock pulse. the peripheral (STA001) that acknowledges has to pull-down (low) the sda line during the clock pulse. the STA001 which has been addressed has to generate an acknowledge after the reception of each byte, oth- erwise the sda line remains at at the high level during the ninth clock pulse time. in this case the m p can gen- erate the stop information in order to abort the transfer. transmission without acknwoledge avoiding to detect the acknowlegde of the STA001, the m p can use a simpler transmission: simply it waits one clock period without checking the STA001 acknowledging, and sends the new data. this approach of course is less protected from misworking. figure 2. validity on the i 2 cbus figure 3. timing diagram of the i 2 cbus sda scl data line stable, data valid change data allowed d99au1031 scl sda start i 2 cbus stop d99au1032 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 12/20 figure 4. acknowledge on the i 2 cbus timing specification figure 5. data and clock figure 6. start and stop symbol parameter minimum time (ns) t cs data to clock set up time 100 t ch data to clock hold time 50 t cwh clock pulse width high 100 t cwl clock pulse width low 100 symbol parameter minimum time (ns) tstart 1,2 clock to data start time 100 tstop 1,2 data to clock down stop time 100 scl 1 msb 23789 sda start acknowledgment from receiver d99au1033 t cs t ch t cwh t cwl sda scl t start1 sda scl t stop1 t start2 t stop2 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
13/20 STA001 figure 7. software specification interface protocol the interface protocol comprises: - a start condition (s) - a chip address byte - a two data bytes - a stop condition (p) ack = acknowledge s = start p = stop "byte by byte" option a "byte by byte" programming mode is also possible when there is no need to use both data bytes to program the chip (for example during the setup of 2nd pll). to use this feature remember that first bit of both data bytes is reserved to chose the destination of the remaining 7 bits. ack = acknowledge s = start symbol parameter maximum time (ns) t d1 ack begin delay 200 t d2 ack end delay 200 msb chip address lsb msb 1st data byte lsb msb 2nd data byte lsb s11000000 ack 1 d6d5d4d3d2d1d0 ack 0 d6d5d4d3d2d1 d0ack p msb chip address lsb msb 1st data byte lsb s11000000 ack k d6d5d4d3d2d1d0ack p sda scl td2 89 td1 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 14/20 p = stop k= destination of the remaining 7bit: k=1 the data byte has the same function of the 1st data byte in the normal programming mode. k=0 the data byte has the same function of the 2nd data byte in the normal programming mode. table 1. first data byte selection table (selection of synthesizer channel) using a 14.72mhz quartz msb lsb rf lo freq. selected units division ratio selected on synthesizer notes d6 d5 d4 d3 d2 d1 d0 from ref1 to lo1 0 0 0 0 1 1 0 1324.8+6*0.46 (1327.56) mhz 360.75 lowest selectable freq. 0 0 0 0 1 1 1 1324.8+7*0.46 mhz 360.875 0 0 0 1 0 0 0 1324.8 + 8*0.46 mhz 361 ------- 0 0 1 1 1 0 1 1338.14 mhz 363.625 first used freq. - - - - - - - 1324.8 + n*0.46 n=(d6..d0) represented decimal number mhz 360 + n*0.125 general freq. generation rule 1 1 0 1 1 1 0 1375.4 mhz 373.75 last used freq. ------- 1 1 1 1 1 1 1 1383.22 mhz 375.875 0 0 0 0 0 0 0 1383.68 mhz 376 ------- 0 0 0 0 1 0 1 1324.8+133*0.46 (1385.98) mhz 376.625 highest selectable freq. 1 0 0 0 1 0 1 1356.54 mhz 368.625 startup presetted data obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
15/20 STA001 table 2. first data byte selection table (selection of synthesizer channel) using a 14.725mhz quartz table 3. second data byte selection table (lock test on both pll, dividers test and if pll test) msb lsb rf lo freq. selected units division ratio selected on synthesizer notes d6 d5 d4 d3 d2 d1 d0 from ref1 to lo1 0 0 0 0 1 1 0 1325.25 +6*0.46015625 (1328.010938) mhz 360.75 lowest selectable freq. 0 0 0 0 1 1 1 1325.25 +7*0.46015625 mhz 360.875 0 0 0 1 0 0 0 1325.25+ 8*0.46015625 mhz 361 ------- 0 0 1 1 1 0 0 1338.134375 mhz 363.5 first used freq. - - - - - - - 1325.25+ n*0.46015625 n=(d6..d0) represented decimal number mhz 360 + n*0.125 general freq. generation rule 1 1 0 1 1 0 1 1375.407031 mhz 373.625 last used freq. ------- 1 1 1 1 1 1 0 1383.229688 mhz 375.75 1 1 1 1 1 1 1 1383.689844 mhz 375.875 ------- 0 0 0 0 1 0 1 1325.25 +133*0.46015625 (1386.450781) mhz 376.625 highest selectable freq. 1 0 0 0 1 0 1 1357.000781 mhz 368.625 startup presetted data msb lsb working mode notes d6 d5 d4 d3 d2 d1 d0 0000000 lock test on rf pll lock flag to be tested: tlck; startup presetted data 0000100 lock test on if pll lock flag to be tested: tlck 0000001l ock test on rf and if pll lock flag to be tested: tlck 0010010 first pll programmable divider test output freq. divided by 16 available on tlck 0011010 first pll reference divider test output freq. divided by 8 available on tlck 0010110 second pll fixed divider test output freq. divided by 2 available on tlck 0011110sec ond pll reference divider test output freq. available on tlck 1000000t est frequency on if pll divider by 1034 division ratio changed to 987 1100000t est frequency on if pll divider by 1034 division ratio changed to 1081 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 16/20 test and application board schematic figure 8. test board schematic diagram note: connect a resistor from10k to 100k between pins padj1 (9) and padj2 (10) so to obtain intermediate gain between 25 and 30 db c24 15nf l5 1nh c5 330pf vcc c41 100pf c8 1nf c15 10nf vcc clk1 u1 STA001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 vp1 sip sin vn1 lni nlni vn1 nc padj1 padj2 enrfosc vp2 tk1 ntk1 vp2 flt1 vn2 xtal1 xtal2 ref xosel tlck rxi nrxi gadj1 gadj2 ce vp3 scl sda vn3 m_clk1 m_clk2 vn4 sop son vn4 agc1 agc2 vp4 ntk2 tk2 vp4 flt2 r3 50 vcc c12 c37 8pf d2 ma372j c11 220nf r9 1k c7 3.3 nf agc1 1:1 c20 10nf clk2 c4 1nf vcc if1 out c13 8pf c28 10nf t3 ldb20c500a1500 1 2 4 5 6 vp4b 1:1 l3 c22 100pf vcc c26 100pf c16 10nf j5 sma 1 2 l1 68nh c36 100nf c39 100pf c2 1nf c17 8pf 1:4 c29 150nf c27 r8 c1 680pf r2 c10 1nf jp1 jumper2 1 2 3 4 c19 100pf j6 sma 1 2 rf in c33 100pf d1 ma372j agc2 r6 18 k vcc c14 8pf r10 d4 hvu355 t2 neosid 553210 1 2 4 5 6 j1 sma 1 2 c23 nrxi out r5 5.6 k rxi out j2 sma 1 2 r14 0 r15 390 if2 in vcc y1 crystal sda c35 1nf ce vcc c6 100nf c9 220nf r7 50 + c31 10uf vcc r11 4.7k l4 1nh d3 hvu355 r17 50 c3 100nf r16 1k vp2b j3 sma 1 2 l2 68nh vcc vp3 jp2 1 2 3 4 vcc scl vp2a vp1 r12 4.7k vcc r1 100k vp4a r13 1k c34 8pf t1 neosid 553200 1 2 4 5 6 r4 100k j4 sma 1 2 t_lock c30 c24 15nf l5 1nh c5 330pf vcc c41 100pf c8 1nf c15 10nf vcc clk1 u1 STA001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 vp1 sip sin vn1 lni c24 15nf l5 1nh c5 330pf vcc c41 100pf c8 1nf c15 10nf vcc clk1 u1 STA001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 vp1 sip sin vn1 lni nlni vn1 nc padj1 padj2 enrfosc vp2 tk1 ntk1 vp2 flt1 vn2 xtal1 xtal2 ref xosel tlck rxi nrxi gadj1 gadj2 ce vp3 scl sda vn3 m_clk1 m_clk2 vn4 sop son vn4 agc1 agc2 vp4 ntk2 tk2 vp4 flt2 r3 50 vcc c12 c37 8pf d2 ma372j c11 220nf r9 1k c7 3.3 nf agc1 1:1 c20 10nf clk2 c4 1nf vcc if1 out c13 8pf nlni vn1 nc padj1 padj2 enrfosc vp2 tk1 ntk1 vp2 flt1 vn2 xtal1 xtal2 ref xosel tlck rxi nrxi gadj1 gadj2 ce vp3 scl sda vn3 m_clk1 m_clk2 vn4 sop son vn4 agc1 agc2 vp4 ntk2 tk2 vp4 flt2 r3 50 vcc c12 c37 8pf d2 ma372j c11 220nf r9 1k c7 3.3 nf agc1 1:1 c20 10nf clk2 c4 1nf vcc if1 out c13 8pf c28 10nf t3 ldb20c500a1500 1 2 4 5 6 vp4b 1:1 l3 c22 100pf vcc c26 100pf c16 10nf j5 sma 1 2 l1 68nh c36 100nf c39 100pf c2 1nf c17 8pf 1:4 c29 150nf c27 c28 10nf t3 ldb20c500a1500 1 2 4 5 6 vp4b 1:1 l3 c22 100pf vcc c26 100pf c16 10nf j5 sma 1 2 l1 68nh c36 100nf c39 100pf c2 1nf c17 8pf 1:4 c29 150nf c27 r8 c1 680pf r2 c10 1nf jp1 jumper2 1 2 3 4 c19 100pf j6 sma 1 2 rf in c33 100pf d1 ma372j agc2 r6 18 k vcc c14 8pf r10 r8 c1 680pf r2 c10 1nf jp1 jumper2 1 2 3 4 c19 100pf j6 sma 1 2 rf in c33 100pf d1 ma372j agc2 r6 18 k vcc c14 8pf r10 d4 hvu355 t2 neosid 553210 1 2 4 5 6 j1 sma 1 2 c23 nrxi out r5 5.6 k rxi out j2 sma 1 2 r14 0 r15 390 if2 in vcc y1 crystal d4 hvu355 t2 neosid 553210 1 2 4 5 6 j1 sma 1 2 c23 nrxi out r5 5.6 k rxi out j2 sma 1 2 r14 0 r15 390 if2 in vcc y1 crystal sda c35 1nf ce vcc c6 100nf c9 220nf r7 50 + c31 10uf vcc r11 4.7k l4 1nh d3 hvu355 r17 50 c3 100nf r16 1k vp2b j3 sma 1 2 l2 68nh vcc vp3 jp2 1 2 3 4 vcc scl vp2a vp1 r12 4.7k vcc r1 100k r16 1k vp2b j3 sma 1 2 l2 68nh vcc vp3 jp2 1 2 3 4 vcc scl vp2a vp1 r12 4.7k vcc r1 100k vp4a r13 1k c34 8pf t1 neosid 553200 1 2 4 5 6 r4 100k j4 sma 1 2 t_lock c30 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
17/20 STA001 figure 9. application board schematic diagram suggested minimum differential rload on rxi and nrxi output 3k l8 6.8nh c23 nr x 1:1 vcc c14 8pf c30 100pf c12 100p c1 680pf c26 clk1 clk2 vcc c2 100nf r f in c24 15nf c16 8pf l6 7.5nh c8 22p c15 2.2p l10 2.2nh j1 sm a 1 2 d4 hvc355b l2 68nh c28 vcc vp2a c4 3.3 nf j2 sm a 1 2 vcc l4 56nh vcc c21 10nf sda r8 1k c25 100pf c13 6.8p c18 100p vp2b l5 100nh c6 10n l7 q1 2sc5096 3 1 2 r11 1k t1 ldb20c500a1500 1 2 4 5 6 vp3 vp4b u1 s+m y012b 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 gnd nc nc gnd gnd gnd out out gnd gnd in in gnd gnd gnd nc nc gnd rxi o r1 10k c34 100pf c3 330pf c10 100p c33 100pf d1 ma2s372 scl c27 150nf agc c7 150nf vp1 r7 4.7k c19 8pf c31 8pf c32 1nf u3 s+m b69813-n1477-a840 3 4 1 2 5 6 io gnd gnd gnd gnd vcc j3 sma 1 2 y1 crystal r2 5.6 k c5 100p d2 ma2s372 r10 390 l9 2.2nh l1 68nh ant +b vcc r9 0 t_ lo ck vcc vcc c9 150nf vcc vp4a c22 100pf r4 33 u2 STA001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 vp1 sip sin vn1 lni nlni vn1 nc padj1 padj2 enrfosc vp2 tk1 ntk1 vp2 flt1 vn2 xtal1 xtal2 ref xosel tlck rxi nrxi gadj1 gadj2 ce vp3 scl sda vn3 m_clk1 m_clk2 vn4 sop son vn4 agc1 agc2 vp4 ntk2 tk2 vp4 flt2 l3 100nh r5 33k c17 10n r3 18 k d3 hvc355b vcc r6 4.7k c20 10nf c11 5p vcc vcc l8 6.8nh c23 nr x 1:1 vcc c14 8pf c30 100pf c12 100p c1 680pf c26 clk1 clk2 vcc c2 100nf r f in c24 15nf c16 8pf l6 7.5nh c8 22p c15 2.2p l10 2.2nh l8 6.8nh c23 nr x 1:1 vcc c14 8pf c30 100pf c12 100p c1 680pf c26 clk1 clk2 vcc c2 100nf r f in c24 15nf c16 8pf l6 7.5nh c8 22p c15 2.2p l10 2.2nh j1 sm a 1 2 d4 hvc355b l2 68nh c28 vcc vp2a c4 3.3 nf j2 sm a 1 2 vcc l4 56nh vcc c21 10nf sda r8 1k c25 j1 sm a 1 2 d4 hvc355b l2 68nh c28 vcc vp2a c4 3.3 nf j2 sm a 1 2 vcc l4 56nh vcc c21 10nf sda r8 1k c25 100pf c13 6.8p c18 100p vp2b l5 100nh c6 10n l7 q1 2sc5096 3 1 2 r11 1k t1 ldb20c500a1500 1 2 4 5 6 vp3 vp4b u1 s+m y012b 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 gnd nc nc gnd gnd gnd out out gnd gnd in in 100pf c13 6.8p c18 100p vp2b l5 100nh c6 10n l7 q1 2sc5096 3 1 2 r11 1k t1 ldb20c500a1500 1 2 4 5 6 vp3 vp4b u1 s+m y012b 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 gnd nc nc gnd gnd gnd out out gnd gnd in in gnd gnd gnd nc nc gnd rxi o r1 10k c34 100pf c3 330pf c10 100p c33 100pf d1 ma2s372 scl c27 150nf agc c7 150nf vp1 r7 4.7k c19 8pf c31 8pf gnd gnd gnd nc nc gnd rxi o r1 10k c34 100pf c3 330pf c10 100p c33 100pf d1 ma2s372 scl c27 150nf agc c7 150nf vp1 r7 4.7k c19 8pf c31 8pf c32 1nf u3 s+m b69813-n1477-a840 3 4 1 2 5 6 io gnd gnd gnd gnd vcc j3 sma 1 2 y1 crystal r2 5.6 k c5 100p d2 ma2s372 r10 390 l9 2.2nh l1 68nh ant +b vcc c32 1nf u3 s+m b69813-n1477-a840 3 4 1 2 5 6 io gnd gnd gnd gnd vcc j3 sma 1 2 y1 crystal r2 5.6 k c5 100p d2 ma2s372 r10 390 l9 2.2nh l1 68nh ant +b vcc r9 0 t_ lo ck vcc vcc c9 150nf vcc vp4a c22 100pf r4 33 u2 STA001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 vp1 sip sin vn1 lni nlni vn1 nc padj1 padj2 enrfosc vp2 tk1 ntk1 vp2 r9 0 t_ lo ck vcc vcc c9 150nf vcc vp4a c22 100pf r4 33 u2 STA001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 vp1 sip sin vn1 lni nlni vn1 nc padj1 padj2 enrfosc vp2 tk1 ntk1 vp2 flt1 vn2 xtal1 xtal2 ref xosel tlck rxi nrxi gadj1 gadj2 ce vp3 scl sda vn3 m_clk1 m_clk2 vn4 sop son vn4 agc1 agc2 vp4 ntk2 tk2 vp4 flt2 l3 100nh r5 33k c17 10n r3 18 k d3 hvc355b vcc r6 4.7k c20 10nf c11 5p vcc flt1 vn2 xtal1 xtal2 ref xosel tlck rxi nrxi gadj1 gadj2 ce vp3 scl sda vn3 m_clk1 m_clk2 vn4 sop son vn4 agc1 agc2 vp4 ntk2 tk2 vp4 flt2 l3 100nh r5 33k c17 10n r3 18 k d3 hvc355b vcc r6 4.7k c20 10nf c11 5p vcc vcc obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
STA001 18/20 application note: the crystal oscillator must have the following features: symbol parameter test condition min. typ. max. unit crystal oscillator (t = 25, vp-vn = 3v) f xtal1 quartz frequency - resonance mode: series - using a 14.72 14.72 mhz f xtal2 quartz frequency - resonance mode: series - using a 14.725 quartz 14.725 mhz p n phase noise d f = 1 khz -120 -118 dbc/hz v dc xtal1, xtal2 common mode dc voltage xosel high vp-1.1 vp-0.9 vp-0.7 v obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
19/20 STA001 tqfp44 (10 x 10) dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.014 0.018 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 0.80 0.031 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 3.5?(typ.), 7 (max.) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 outline and mechanical data obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 20/20 STA001 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)

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